The present invention relates to semiconductor device fabrication technology, and more particularly, to a semiconductor device with a vertical channel transistor and a method for fabricating a semiconductor device with a vertical channel transistor.
Recently, there has been an increasing need for sub-40 nm memory devices to increase the degree of integration. However, it is very difficult to realize a downscaled memory device having a line width of 40 nm or less using a typical planar or recessed gate transistor having an 8F2 or 6F2 cell architecture (where ‘F’ represents a minimum feature size). Therefore, dynamic random access memory (DRAM) devices having 4F2 cell architectures are now required since they improve the degree of integration by 1.5 to 2 times without scaling down. To this end, a vertical channel transistor has been suggested.
In a vertical channel transistor, a surround type gate electrode is formed to surround an active pillar that extends vertically on a semiconductor substrate, and source and drain regions are formed in upper and lower portions of the active pillar over and under the gate electrode, respectively, so that a channel is vertically formed. Therefore, even though the transistor area is reduced, the channel length can be maintained.
FIG. 1A illustrates a perspective view of a typical memory device including vertical channel transistors. FIG. 1B illustrates a plan view of a connection between a word line and a gate electrode in the typical memory device.
Referring to FIGS. 1A and 1B, a gate dielectric layer 13 and a gate electrode 14 surround an outer wall of a pillar 12 formed over a substrate 11. A storage node 15 is connected to an upper portion of the pillar 12, and a buried bit line 16 is provided in the substrate 11. A word line 18 is connected to the gate electrode 14 via a barrier metal 17, and extends in a direction so as to cross the bit line 16. An insulation layer 19 is formed between the storage node 15 and the gate electrode 14. The gate dielectric layer 13 may be formed between the substrate 11 and the gate electrode 14.
In the typical memory device, a polysilicon layer is used as the gate electrode 14, and a metal layer is used as the word line 18. Accordingly, a current flowing through the word line 18 is affected by the polysilicon layer used as the gate electrode 14 as well as the metal layer used as the word line 18 because the word line 18 and the gate electrode 14 are connected in series.
However, the current does not only flow through the word line 18; rather, it flows through both a small area of the gate electrode 14 and a large area of the word line 18 (see I1 and I2 of FIG. 1B). Therefore, a total sheet resistance (RS) of the word line 18 dramatically increases due to the small area of the gate electrode 14, making it difficult to realize a high-speed memory device.